In recent years, a DRAM being a typical memory LSI has been manufactured by adopting a so-called `stacked capacitor structure` wherein a capacitor (or capacitance element) for storing information is arranged over a MISFET (Metal Insulator Semiconductor Field Effect Transistor) for selecting a memory cell, in order to compensate for that decrease in the quantity of storage charges (electric charges to-be-stored) of the information storing capacitor which is attendant upon the microfabrication of the memory cell.
On the other hand, in a logic LSI of high performance, the adoption of a so-called `silicidation technique` wherein a refractory metal silicide layer of, for example, CoSi.sub.2 (cobalt silicide) or TiSi.sub.2 (titanium silicide) is formed on the surfaces of the source and drain of a MISFET has been promoted as a measure to suppress those increases in the resistances of the source and drain which are attendant upon the microfabrication of contact holes for respectively connecting the source and drain with wiring lines.